Design of a Pipelined 8b 10MSPS Analog To Digital Converter from System to OTA
Russell Mohn, Member, IEEE
Abstract
This paper is a summary of the design process of an 8-bit 10MSPS pipelined analog to digital converter (ADC). The intended focus of the project was the design of the operational transconductance amplifier (OTA) that is the heart of the switched capacitor circuits that perform functions such as sample-and-hold and amplification by 2. It is the performance of these functional blocks that determine the performance of the whole ADC. The ADC simulated performance was 7.0b ENOB while consuming 56.9mA from a 1.8V supply.
I. Introduction
There is nothing technically novel in this work. Working pipelined ADCs were designed and aptly explained 20 years ago in references [1] and [2]. The design of an OTA is not new either; two simple and direct designs of fully differential OTAs are presented in [3] with explanations of the design choices and a thorough list of measured circuit metrics, such as DC gain, power consumption, and unity gain frequency. However, the tools of design have changed since those papers were published, and this work aims to elucidate a design method using Matlab/Simulink in addition to a traditional SPICE simulator for the system verification of the ADC. After the specifications for blocks have been set by system level simulation, circuit level design was done with SPICE. In this project, no chip was manufactured, so there are no measured data to explain. However, there is a plethora of data output from design simulations available for explanation.
II. Background - Purpose of an ADC
Analog signals are analogous to real physical signals, for example, heartbeats, voices, or music. They are continuous in time and in amplitude. Digital signals are discrete in time and in amplitude. ADCs convert analog signals to their equivalent digital representations. There are some physical limitations during this conversion process, an important one is that the sampling rate must be twice the signal bandwidth for alias-free representation of the signal; twice the signal bandwidth is called the Nyquist rate. There are at least three different architectures for ADCs, namely flash, pipelined, and sigma-delta. Both flash and pipelined converters operate at a sampling rate equal to the Nyquist rate. A sigma-delta ADC works by sampling the incoming data at a rate greater than the Nyquist rate. Sigma-delta ADCs are useful for lower bandwidth signals that need high resolution. For example, a sigma-delta ADC can be used to digitize a music signal with 24-bits of resolution. A flash ADC converts an analog signal to it’s digital equivalent immediately at the converter’s sampling rate. Flash converters are useful for high data rate applications that require a resolution of 6b or less; at more than 8b resolution, a flash converter becomes very large in chip area and power consumption. Similar to a flash converter, a pipelined converter also works at the Nyquist rate, but the digital representation of the input analog signal is not available immediately after one sample period. There is latency from the input of the pipelined ADC to its output. A pipelined ADC divides the task of conversion into identical sub-tasks that are carried out by identical functional blocks in a pipelined fashion. For example, the first functional block takes the held value of the input analog signal and decides whether the signal is above a reference voltage. If it is above the reference voltage, the bit for that stage is set to “1” and twice the input signal minus the reference signal is passed to the next stage. If the input is not above the reference voltage, the bit for that stage is set to “0” and twice the input signal is passed to the next stage. In this way, all the bits of the digital code representing the analog data are available after the signal has passed through all the stages of the pipeline. To assemble all the bits such that they come out of the ADC at the same time, they are aligned in time with chains of D flip-flops clocked at the converter’s sampling clock. The pipelined ADC is well suited for applications that require a Nyquist rate conversion up to hundreds of mega-samples per second (MSPS) and resolutions in the range of 8-bits or more.
The primary objective of this work was to design the OTA and switched capacitor amplifier to be used in an 8b 10MSPS ADC. In addition to that circuit design, a significant amount of ADC system modeling with Matlab/Simulink and Verilog-A was done to lay the groundwork for the circuit specifications. The basic design objectives for the ADC are listed in Table 1. Specifically, the power supply is a single supply at 1.8V; the target process technology is a popular 0.18um CMOS process, and the conversion rate is 10MSPS. This paper presents the ADC system design, then the circuit design for the switched capacitor switches and capacitors, the circuit design for the OTAs, and finally the full ADC simulation results.
III. ADC Design with Simulink/Matlab and Verilog-A
The fastest way for me to verify that the pipelined architecture works as an ADC was to build a model of it in Simulink as shown in Figure 1. In Figure 1, one can see the identical functional blocks connected in a pipelined fashion with one output feeding the next block in the pipeline and another output feeding a delay element that aligns in time the correct output bits. In Figure 2, the model for a single stage of the pipeline is shown; this model attempts to model some of the anticipated circuit imperfections such as the noise voltage seen at the input of the stage as created by the output noise of the previous stage, the finite DC gain of the OTA, and the gain error of the amplifier. The amplifier is designed to amplify with a gain of 2V/V exactly; any deviation from a gain of 2V/V is a gain error. Capacitor mismatch or a non-zero offset voltage in the OTA may cause gain errors. A fully-differential design for the OTA and amplifier was chosen to balance the errors created by injected charge from the switches into the capacitors as they are switched. This model makes it easy to apply these imperfections one-by-one with all other imperfections removed to see the effect of each imperfection on the total ADC performance. In addition, the trend of the imperfections can be changed as well. For example, there may be a component of the gain error that is common to all 8 stages in addition to a random gain error that is particular to each single stage. The metrics chosen for the ADC performance were its effective number of bits (ENOB), which is ideally 8b, and its differential non-linearity (DNL), which is ideally 0LSB. DNL bounded by 1LSB assures a monotonic input-output ADC transfer characteristic.
In Figure 3, the DNL and ENOB is plotted for the cases of the OTA open loop DC gain (A0) being 20dB, 40dB, 60dB, and 80dB. For open loop gains of 20dB and 40dB the ENOBs are 4.2b and 7.1b, respectively. For an open loop gain of 60dB, the ENOB goes up to 7.9b. Thus, 60dB of open loop DC gain is sufficient to meet the specifications; this is of course assuming that there are no other imperfections contributing to the ADC non-linearity.
The input noise voltage of each stage was changed from a mean squared value of 5e-4V2 to 5e-8V2 in Figure 4. This is the variance of the noise integrated from 1Hz to 10GHz. The source of this input noise voltage is the output noise voltage of the previous stage. This is random electrical noise created by the circuit elements in the OTAs. In this system model, the filtering caused by the resistors and capacitors in the circuit implementation of the amplifier is not modeled, so it should be an overestimate for the system’s tolerance to random noise. The results show that the noise level predominantly affects the spectrum of the ADCs output, showing that a mean square noise voltage of 5e-8V2 will give an ENOB of 7.9b, while a mean squared noise voltage of 5e-4V2 results in an ENOB of 3.6b. Thus the target input noise mean squared value is 5e-8V2.
The effect of an equal gain error applied to each stage is shown in Figure 5. The ADC performance is very sensitive to the gain error. With just a 1% gain error applied to each stage, the ENOB drops to 7.2b and the DNL is barely within the 1LSB specification. This implies that the capacitors in the switched capacitor circuits should be made large to match them better and minimize the systematic gain error.
IV. Switch Circuit Design
After the target specifications for the amplifier were determined by simulating the Simulink model, the schematics for the entire ADC were entered in the Cadence design environment. The top ADC schematic is shown in Figure 7; the schematic for a single stage of the ADC including a 1-bit digital-to-analog converter built with a comparator and latch verilog-A components is shown in Figure 8; the schematic for the switched capacitor amplifier is shown in Figure 9.
The full-scale voltage was chosen to be 1V. Since the design is fully differential this means that the input differential pair will see a range of signal voltages from 0V to 500mV. With a power supply of 1.8V, and assuming that all devices are biased in saturation with an approximate Vgs-Vt of 200mV, there is still 1V of room for the transconductance devices even if is has a cascoded PMOS current mirror load and cascoded NMOS current mirror bias. This choice of power supply voltage and full-scale voltage allows for some flexibility in the OTA design. The full-scale voltage of 1V gives an LSB voltage of 3.9mV.
In [1] the noise variance sampled on the capacitor in the amplifier is given by 4/3*KT/C. For a 500fF sampling capacitance, the noise variance is 1.1e-8V2 which is below the value, 5e-8V2, determined by system modeling. The maximum allowable time for the amplifier to settle is 50ns which is one half the clock period; it is desirable to have the amplifier settle within 0.25*LSB well below this 50ns upper limit. An RC circuit settles to within 99% of its final value in approximately 5*RC seconds. The closed switch resistance for a maximum Vds of 500mV is calculated in Figure 6 as 265W. This gives a 5*RC product of 0.7ns which will meet the specification.
V. OTA Circuit Design
After choosing the values for the sampling capacitors and designing the switches for the switched capacitor amplifier, a single stage differential pair was simulated to determine how much gain it could provide as shown in Figure 10. An NMOS differential pair was chosen because NMOS transistors have approximately 3 to 5 times higher mobility than PMOS transistors; therefore, an equivalent transconductance could be created for a device that is 3 to 5 times smaller than its equivalent PMOS. A smaller device means smaller parasitic capacitances and smaller parasitic capacitances means less capacitive division when the OTA is used with capacitive feedback. It is desirable to design such that only the feedback capacitors and switch resistors determine the behavior of the amplifier. Also, the NMOS was chosen in hopes that it would a more efficient transconductor – the gain of the stage should be higher for an equivalent bias current relative to the PMOS. The folded cascode circuit was chosen because the output common mode level can easily be set equal to the input common mode level; in this case, the common mode level was nominally designed for mid-rail, 900mV. The open loop DC gain of the circuit in Figure 10 was 57dB with a bias current of 1.23mA. Such a simple circuit nearly meets the 60dB of gain from the system simulations. A simple one-stage design is attractive because it can be compensated for stability simply by adding additional capacitance from output to ground.
In an attempt to increase the gain of the single stage the output current mirror was cascoded as shown in Figure 11. The current mirror bias for the input differential pair is also cascoded which should increase the OTA’s common mode rejection. Since the gain of the single-stage amplifier is the product of the transconductance of the input differential pair and the output impedance, the idea was to increase the output impedance by the gm*Ro of the additional cascode device. The circuit’s simulated gain of 58dB for a bias current of 0.94mA shows that it is more efficient than it’s simpler sibling, but not by much. Adding a second stage as shown in Figure 12 increased the DC gain to 82dB for a bias current of 2.12mA, but this circuit was not chosen because the output common mode level is very sensitive to the biasing of the output stage. Thus, the simplest circuit was chosen and the common mode feedback circuit was added as shown in Figure 13.
The common mode feedback detector is a 100kW resistor in parallel with a 1pF capacitor. The large resistance value was chosen so it would load the amplifier as little as possible. The small 100W resistor in series with the capacitor is used to turn the phase of the CMFB frequency response down at high frequencies as shown in Figure 17. The common mode feedback amplifier was designed in parallel to the forward gain amplifier as suggested in [3]. In fact, the CMFB amplifier was designed with a differential pair that was half the aspect ratio and bias current of the forward gain differential pair. Simulations of the verilog-A OTA model showed that the CMFB loop had a bandwidth equal to the forward gain loop, with a single pole roll-off. Also, the verilog-A OTA model confirmed that an OTA with 60 degrees of phase margin has its second pole at about twice the unity gain frequency. The verilog-A is an idealized OTA model; however, some inspiration can be derived from it. Comparison of the gain-bandwidth product in Table 2 shows that they are on the same order of magnitude, but the differential gain-bandwidth (600MHz) is roughly 3x that of the CMFB loop (200MHz). It was difficult to extend the CMFB gain-bandwidth. The output values produced by a DC sweep of the input differential voltage shown in Figure 14 shows that the amplifier’s linear output range is from 0.36V to 1.4V, which corresponds to a differential input of approximately –2mV to 2mV. Figure 15 shows differential gain as a function of the DC differential input; this underscores the importance of keeping the OTA’s offset voltage below 10mV, because for offsets greater than 10mV the gain drops drastically.
In Figure 18, the test setup for the CMFB loop is shown. A copy of the CMFB amplifier was inserted into the OTA to stabilize the output common mode level and bias the circuit correctly while also posing as an equivalent load to the common mode detector. Then, the loop was broken at the input to the original CMFB amplifier, and both DC and AC sources were used to characterize the DC response (Figure 20) and frequency response (Figure 19). The CMFB loop gain is only 4dB; the frequency to note is where it crosses below 0dB. At this frequency, the phase is still 90 degrees away from 0 degrees, so the loop is stable. When the output of the loop arrives at the input with 0 degrees of phase shift, it can add in phase to the input and oscillate. The DC sweep of the CMFB control voltage shows that there is a peak in the gain when the common mode level is 945mV rather than the 900mV for which the circuit was originally designed. It is acceptable to adjust the common mode level to 945mV because there was margin in the output and input bias voltage levels and all devices will still remain in saturation.
VI. Switched Capacitor Amplifier Simulation Results
Simulated full-scale step responses of the switched capacitor amplifier are shown in Figure 22 and Figure 23. The step responses show some ringing which is indicative of insufficient phase margin in the OTA when configured with feedback capacitors and switches. This could likely be improved by increasing the switch resistance or the sampling capacitance or both. A better approach would be to re-examine the stability of the OTA in the context of the switched capacitor circuit. Figure 23 shows there is gain error in the amplifier. The gain error is (1000mV – 986.5mV) / 1000mV * 100% = 1.35% which from the system simulations immediately drops the ADC ENOB to at most 7.16b. The output noise of the amplifier was simulated when the amplifier was in amplify mode and the results are in Figure 24. Integrating the squared noise voltage density from 1Hz to 10GHz and taking the square root gives the RMS noise voltages reported in Table 3. The typical value of 255.7uV,rms corresponds to a noise variance of 6.5e-8V2 which from system simulations is not catastrophic to the ADC performance but above the target value of 5e-8V2.
VII. ADC Simulation Results
Using the transistor-level circuit designs for the switches and the OTAs the entire ADC was simulated with a 365kHz sinusoid input with a 490mV amplitude. The 8 bits out of the ADC were mapped to single integer values with a Verilog-A signed digital-to-analog converter. A portion of the output signal is shown in Figure 25. The output looks like a sinusoid, which is promising. The spectral analysis and DNL are shown in Figure 26 and Figure 27, respectively. The ENOB is 7.0b which is expected from the gain error of the switched capacitor amplifier, and the corresponding DNL stayed within 1LSB which indicates that the ADC is monotonic. The current consumption for the whole ADC during a portion of the transient simulation is shown in Figure 28, and this was used to calculate the average current consumption which is 56.9mA. This is an underestimate for the current consumption because it is a schematic simulation that does not include the current needed for the clock drivers and the input sample-and-hold circuit.
VIII. Conclusions
An 8b pipelined 10MSPS ADC was designed from the system level down to some of its critical circuits. The OTA used in the switched capacitor amplifier and the switches and capacitors were designed with considerations for noise and amplifier settling time given the conversion rate of 10MSPS and chosen full-scale voltage of 1V. The stringent requirements of the gain error necessitate an amplifier with accurate gain, such as that of a switched capacitor amplifier where the gain can be set by the matching of capacitors. Switched capacitor amplifiers necessitate a fully differential OTA structure to minimize the effect of charge injection from switches. A fully differential OTA necessitate the design of an effective common mode feedback circuit. A more focused effort on the design of the OTA and the CMFB circuitry would improve the simulated performance of the overall ADC.
Table 1. ADC basic design specifications (back)
Table 2. OTA simulated performance over corners (back)
Table 3. Simulated performance of switched capacitor x2 amplifier (back)
Table 4. Simulated performance of 8b pipelined ADC with fclk=10MHz (back)
Figure 1. Matlab/Simulink model of 8b pipelined ADC (back)
Figure 2. Model of single stage of pipeline including circuit imperfections (back)
Figure 3. Effect of OTA open-loop DC gain (A0) on ENOB and DNL (back)
Figure 4. Effect of input noise voltage variance (Vn2) on DNL and ENOB (back)
Figure 5. Effect of gain error on DNL and ENOB if all stages have equivalent gain error (ideal gain = 2V/V) (back)
Figure 6. Switch resistance with Vds swept 0V .. 500mV for W/L = 10*1um/0.18um (back)
Figure 7. Schematic of the 8b pipelined ADC (back)
Figure 8. Schematic of 1-bit verilog-A ADC and switched capacitor sample and amplify by 2 (back)
Figure 9. Schematic of the switched capacitor sample and amplify by 2 (back)
Figure 10. Single stage folded cascode OTA with simple current mirror load (back)
Figure 11. Single stage folded cascode OTA with cascoded current mirror load (back)
Figure 12. Two-stage OTA with 82dB of DC gain (2.12mA total quiescent current) (back)
Figure 13. OTA design with common-mode feedback circuit chosen for ADC (back)
Figure 14. OTA differential DC input-output transfer curves (back)
Figure 15. OTA DC gain as a function of the input differential DC voltage (back)
Figure 16. OTA differential frequency response (open loop) (back)
Figure 17. OTA common mode frequency response (open loop) (back)
Figure 18. Test setup for the CMFB loop (back)
Figure 19. OTA CMFB loop frequency response (back)
Figure 20. CMFB loop DC input-output transfer characteristic (back)
Figure 21. CMFB loop gain vs. DC value of CMFB control voltage (back)
Figure 22. Switched capacitor x2 amplifier transient result for b = 0 (left) and b = 1 (right) (back)
Figure 23. Switched capacitor x2 amplifier transient simulation with full-scale input step (back)
Figure 24. Switched capacitor x2 amplifier output noise spectral density (back)
Figure 25. 8b ADC transient output with input sinusoid at 365kHz, amplitude = 490mV (back)
Figure 26. SNR, SINAD, and ENOB for 8b ADC with 365kHz input sinusoid, amplitude = 490mV (back)
Figure 27. DNL of 8b ADC calculated by histogram method with sinusoid input (back)
Figure 28. Current consumption of 8b ADC, fclk=10MHz, 365kHz sinusoid input with amplitude = 490mV (back)
References
[1] B. S. Song, M. F. Tompsett, and K. R. Lakshmikumar. A 12-Bit 1-Msample/s Capacitor Error-Averaging Pipelined A/D Converter. IEEE Journal of Solid-State Circuits, pgs. 1324-1333, December 1988.
[2] S. Lewis and P. Gray. A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter. IEEE Journal of Solid-State Circuits, pgs. 954-961, December 1987.
[3] M. Banu, J. Khoury, and Y. Tsividis. Fully Differential Operational Amplifiers with Accurate Output Balancing. IEEE Journal of Solid-State Circuits, pgs. 1410 – 1414, December 1988.