Design of a 802.11b Zero-IF LNA+Mixer
Russell Mohn, Member, IEEE
This paper is a summary of the design procedure of three key circuit blocks in a zero-IF receiver targeted for wireless LAN (802.11b) specifications, namely the LNA, mixer, and LO buffer. Pertinent simulated results for the LNA and mixer are 22.8dB voltage gain, 9.2dB double-sideband noise figure, 8.3mA DC current consumption from a 1.8V supply, and IIP3 of -10.7dBm.
Wireless local area networks (LANs) are a ubiquitous part of our daily lives. They are attractive because they allow portable devices such as laptops to connect to larger networks whenever they are within range (~38m) of a wireless access point. The standard upon which wireless LAN is built is IEEE 802.11 which specifies 11 unique channels each with a 22MHz bandwidth in the spectrum from 2400MHz to 2483MHz. The channel spacing is 5MHz which means there is significant overlap between channels.  Devices employ direct sequence spread spectrum (DSSS) to allow for multiple access to the channels. As a result, the transmission spectral mask is very important to prevent one channel from interfering with its neighbors. In the receiver, linearity is very important because high power out-of-band signals may de-sensitize the receiver. In , the sensitivity level of a receiver is given by:
II. Overall Design Approach
The primary objective of this design project was to design an LNA, mixer, and local oscillator (LO) buffer that meet the specifications for 802.11b while minimizing the receiver’s current consumption. The circuits will be integrated on a single chip; therefore, the LNA and mixer function can be considered as one unit and the interface between the two circuits is entirely up to the designer. The design was carried out in stages. First, the LNA was designed and characterized on its own; its simulation results are shown in Table 1. The LNA input sees signals a range of power from -76dBm to -10dBm; most of the time, the LNA behaves as a small-signal amplifier and small-signal circuit analyses in SPICE like AC, and NOISE were used to design the LNA. To simulate the large-signal behavior of the LNA to determine the compression point or IIP3, periodic steady state (PSS/PAC) analysis was used. Periodic steady state analysis can account for the effects of a circuit’s changing operating point caused by large signals. After the LNA met the performance specifications, its output impedance was simulated by driving the output of the LNA with an AC voltage source and measuring the input current. This output impedance was used as the source impedance for the RF port of the mixer during the mixer design. The mixer and LO buffer were designed and tested together; the mixer simulation results are in Table 2. The mixer load was 5pF (single-ended) which is supposed to model the input impedance of the next filtering stage of the receiver which is not in the scope of this project. Finally, the LNA output was used to drive the RF port of the mixer and the LO buffer output was used to drive the LO port of the mixer as shown in the testbench schematic in Figure 5, and the combined functions of low noise amplification and frequency translation were simulated, and the results are given in Table 3.
III. LNA Design
The LNA schematic shown in Figure 2 is a differential pair with inductor source-degeneration and additional capacitance from gate to source to tune the input. I initially wanted to build the LNA without inductors to reduce the chip area, but the noise figure was over 7dB, the gain was 9dB and the current consumption was around 8mA - so the specifications were not close to being met and the current consumption was high. Inspired by the low current (~4mA) and low noise figure (1.7dB) reported in , I abandoned the idea of an inductor-less LNA, and replaced the source degeneration resistors with inductors. This topology is well-known and commonly used for narrow band LNAs. The input impedance was determined through small-signal analysis as:
where L1 is the bondwire inductance, Ls is the source degeneration inductor, Cgs is the total capacitance from gate to source of the input NFET, and gm is the small-signal transconductance of the NFET. To make the input impedance look like 50O (differentially, or 25O single-ended), the free design variables are Ls, Cgs, and gm. The source degeneration inductor size has a maximum limit set by what can feasibly fit on a chip; I aimed to keep the inductor less than 6nH. In , it is explained that the Q of the tuned combination of inductors and capacitance should be kept relatively small (2 .. 3) to prevent the input matching from being too sensitive to having the exact values for inductors and capacitors, so I chose Q=3. The voltage gain is Gm*R, and for a target value of 17dB (7.1V/V), with 200O load resistance, the input Gm is 36mS; with Q=3, the NFET gm needs to be ~Gm/3 = 12mS, at least. After sweeping the bias current of the LNA, I found that the specification for noise and gain were met by consuming between 2.5mA and 3mA with the input device biased with gm=20mS. The simulated results for the LNA in Table 1 show that the NF is 1.5dB which is 1dB below specification and the voltage gain is 18dB which is about 4dB over specification. To increase the reverse isolation magnitude above 25dB I had to reduce the Cgd of the input NFETs by cutting their total width. Every change to the LNA necessitates re-confirming the noise, gain, linearity, and input matching.
IV. LO Buffer and Mixer Design
The purpose of the LO buffer is to make sure that the oscillations from the VCO have a well-controlled amplitude when they arrive at the LO port of the mixer. The conversion gain, noise, and linearity of the mixer can be drastically affected by the amplitude and shape of the LO waveform driving the LO port. I chose an active double-balanced mixer shown in Figure 4 because the required conversion gain was 8dB and the inputs at both ports needed to be differential. A double-balanced mixer topology eases image-rejection filtering requirements for quadrature modulated RF signals. In addition with near perfect matching in the switching devices and very symmetric LO and inverted LO signals, the LO feedthrough can be made very small with this topology; the simulated result in Table 2 is < 1mVpp where the device width mismatch between devices in differential pairs was assumed to be 1%. The LO buffer circuit topology was chosen for its ease of design and flexibility in drive strength. The input differential pair rejects common mode noise on the VCO’s differential output. The self-biased inverting amplifier and the successive inverters are there to square up the VCO’s sinusoidal output and provide enough drive strength for the mixer’s switching devices. The idea is to turn the mixer’s switching devices on and off as fast as possible so the sampling action is impulsive which minimizes the noise contribution of the switches to the output signal. The mixer is made up of a common-mode tail current source, a resistively source degenerated differential pair for the RF input, and two pairs of switching FETs for the LO. The differential pair for the RF input was biased in triode, so they behave as voltage controlled resistors. Increasing the Vds of the pair and pushing them more towards saturation improved the linearity of the mixer, but at the cost of conversion gain. The primary trade-off in mixer design was between the conversion gain and linearity. If the conversion gain met specification the linearity did not and vice-versa. The mixer needs to be able to accept fairly large signals because of the amplification provided by the preceding LNA. The length of the RF input differential pair was made 3x the minimum length for the technology; this was done to minimize short-channel effects and improve their linearity.
V. RX Chain Simulation Results
Since this is a single-chip integrated circuit design, the output impedance of the LNA and the input impedance of the mixer do not have to be 50O; it is sufficient to match them at a higher impedance if the overall LNA and mixer function meets specifications. The testbench for the LNA driving the mixer is shown in Figure 5, and the simulation results for the testbench are given in Table 3. The first thing to notice in the results is that the circuits do not work over corners; this is because the DC biasing for all 3 circuits is not robust against variations in process, voltage and temperature. Each circuit derives its DC biasing from a reference current, and if this reference current was derived from a bandgap reference voltage and reference generator, it would be possible to make the circuits functional over PVT variations. In Figure 6, the transient simulation waveforms show a 600mVpp LO signal at 2400MHz being mixed with a 20mVpp RF at 2404MHz and the resulting 4MHz baseband signal with amplitude 275mVpp. The overall RF gain of the RX path was 22.8dB which meets the specification of 22dB, and the noise figure for the LNA+mixer is 9.2dB which also meets the noise figure specification of 12.5dB. However, while the gain and noise performance of the receiver met specification, the IIP3 is only -10.7dBm. The maximum input signal for 802.11b is -10dBm, and if this receiver design saw an input of -10dBm, the 3rd order intermodulation products at the output of the mixer would be equal in power to the signal, which is unacceptable. The mixer’s IIP3 needs to be improved.
A cursory description of the design process of an LNA and mixer with LO buffer for 802.11b has been made. The LNA circuit topology is an inductively source-degenerated differential pair with resistor load; the mixer is a conventional active double-balanced type; the LO buffer is a differential pair with self-biased inverting amplifier and scaled inverters. The specifications for noise figure and gain can be met with these circuit choices while consuming 8.3mA (DC), but it is doubtful that the -10.7dBm IIP3 is sufficient for the standard. Further improvement needs to be made in the linearity of the mixer, and perhaps some of the gain could be pushed from the LNA into the mixer.
Table 1. LNA simulated performance summary (back)
Table 2. Mixer simulated performance summary (back)
Table 3. LNA + mixer (+LO buffer) simulated performance summary (back)
Figure 1. RX level diagram
Figure 2. LNA schematic (back)
Figure 3. LO buffer schematic
Figure 4. Mixer schematic (back)
Figure 5. LNA + mixer (+LO buffer) testbench schematic (back)
Figure 6. LNA + mixer transient simulation result showing successful downconversion (back)
Figure 7. LNA + mixer conversion gain and IIP3 (QPSS+QPAC result)
Figure 8. LNA + mixer noise figure (DSB)
Figure 9. In-band IM3 for LNA + mixer (two -27dBm interferers at RF input, 2410MHz and 2414MHz)
Figure 10. Out-band IM3 for LNA + mixer (two -35dBm blockers at 2437MHz and 2467MHz)