Design of a 250MSPS 4-bit Flash ADC

Russell Mohn

ADC Simulated Summary

Sample and Hold Design

Since the Vlsb = (2.5V – 1.25V) / 2^4 = 78.1mV, the required input capacitance based on the quantization noise power is 9.7aF (for operation up to 85C). This calculations is given by: C>=12kT*2^N/VFS^2, where N=4bits, full scale voltage is 1.25V, and the temperature is 85C. This means that even for a very small capacitor the quantization noise of the converter will dominate over the thermal noise of the sample and hold circuit. So there is basically no lower bound on the sampling capacitor size. The upper bound on the sampling capacitor is set by the bandwidth of the input signals which dictates the required settling time. For an ADC sampling frequency of 250MSPS, the input signals are band-limited to the Nyquist frequency, 125MHz. It is desired to have the sample and hold circuit settle to within 1LSB of its final value in half the sampling period; half the sampling period is 2ns. The worst case settling time will be for a full scale step from 1.25V to 2.5V. The final value will be reached in 2.774 time-constants because –1250mV*e^-x = -78mV gives x = 2.774, which is the ratio of time to RC time constants. Setting time = 2ns, the RC time constant must be less than 721ps. Example values for R and C are given below:

C R

10pF 72.1ohm

1pF 721ohm

100fF 7.21kohm

10fF 72.1kohm

The resistance given here is the resistance of the switch when it is in the closed state (sampling). When the switch is in the open (hold) state, it is desirable to have the switch resistance as large as possible to isolate the sampled charge and the comparators from the input signal. It is desirable to make the capacitor as large as possible, given chip area constraints, because the larger capacitance will minimize the voltage shifts caused by charge re-distribution when the clock suddenly turns switches on and off. This is seen by examining the definition of capacitance, voltage = charge / capacitance, which means that for a given sudden shift of charge, the sudden change of voltage will be less for larger capacitances. Initially, 1pF was chosen as the sampling capacitor size. The test setup in Figure 1 was used to size the input switch by setting the transistor widths the variable ‘wx’ and sweeping wx from 1um to 10um. The results shown in Figure 2 say that for transistor widths = 3.4um, the switch resistance will be around 700ohm, which satisfied the settling time requirement. The switch resistance over the input voltage range is also important for the linearity of the ADC; if the resistance depends strongly on the input voltage, the settling time will change which will introduce non-linearity in the ADC. In Figure 3, the switch width was increased to 4um, and the switch resistance stays less than 700ohm over the input voltage range.

A CMOS switch was chosen because it helps mitigate the effect of charge injection when the switch changes from closed mode to open mode. With just a PMOS device as the switch, the hold pedestal moves by 8.8mV when the switch opens, shown in Figure 4. In Figure 5, the CMOS switch is used for the same setup and the hold pedestal is reduced to 1.86mV. In Figure 6 and Figure 7, the effect of connecting the SAH to the clocked comparators is evident. Without the clocked comparator as a load the sample and hold output is ideal. When the clocked comparator is connected, the act of clocking the comparator disrupts the sampled voltage at the input to the comparator. If the disruption is constant for every sample, it will appear as an offset and gain error. A buffer inserted between the SAH and the comparator is another option as well, but it was omitted for the sake of speed in the design and simplicity.

Clock Timing

It is desired to clock the comparator when the SAH is fully settled and holding a constant voltage. The comparator has setup and hold requirements, which means the voltage at the instant the clock edge transitions from LO to HI must be persistent at the input for the setup time and must remain persistent after the transition for the hold time. I did not simulate the setup and hold times of the comparator, but a complete design would include this sort of analysis. To allow the SAH to settle before the comparator is clocked, the SAH clock and comparator clocks have the phase relationship in Figure 9. The clock rise and fall times were kept below 500ps for the SAH and comparators by making scaling the buffers with a ratio of 3x for subsequent buffers.

ADC Design and Results

The ADC top schematic is shown in Figure 10, and the testbench is in Figure 11. I increased the sampling capacitor from 1pF to 3pF and reduced the sampling switch resistance by changing the FET multiplier factors from 1 to 3 to get better dynamic performance from the ADC. I suspect the comparators’ disturbance of the SAH was too sever with 1pF, and using 3pF mitigated that disturbance. After making that update, an ENOB of 3.9b was achieved for input full scale sinusoids of 2MHz and 12.5MHz, shown in Figure 13 and Figure 14.

Future Improvements

This ADC was designed assuming a stable reference voltage was available; in the future this voltage reference would have to be designed. Furthermore, the resistors in the Kelvin divider used to generate the reference voltage trip points are on the order of 5ohms, which for a voltage drop of 1V and 15 resistors will give current consumption on the order of 13mA, which might be able to reduced. Power consumption was not simulated either in this design, and that would be a must for the next iteration.

Figure 1. Same and hold test setup - used to determine switch width (back)

Figure 2. Switch resistance over FET width
Figure 3. Switch resistance over input voltage range (back)

Figure 4. Sample and hold output with just 1 PMOS switch
Figure 5. Sample and hold output with CMOS switch (back)

Figure 6. Sample and hold of input sine, with no load on capacitor (open circuit)
Figure 7. Sample and hold of input sine, with 15 comparators connected to capacitor (back)

Figure 8. Clock timing buffers
Figure 9. Clock timing - SAH rising edge is delayed ~1ns relative to COMP rising edge (back)

Figure 10. ADC top schematic - flash architecture (back)

Figure 11. Flash ADC testbench - source is ramp for INL and DNL test (back)

Figure 12. Initial ADC simulation result for input ramp - all codes appear -> function OK

Figure 13. Output spectrum for 2MHz input, full scale
Figure 14. Time-domain signal used to create output spectrum (back)

Figure 15. Output spectrum for 12.5MHz input, full scale
Figure 16. Time-domain signal used to create output spectrum

Figure 17. Time-domain output for 125MHz input sinusoid --> ADC is functional at this speed.

Figure 18. INL and DNL simulated by applying a ramp with N=100 samples per step from Vmin to Vmax